Cache memory is volatile memory and requires power to retain data stored in the memory. The more data that is stored in a cache memory, the more power drawn by the cache memory. To conserver power, portions of the cache memory not occupied by active data, or storing data no longer needing to be cached, can be powered off, while only portions of the memory storing data that needs to be cached remain powered.
To enable powering down portions of a cache memory, the inactive or no longer needed data stored in cache must be “flushed” to store that data in another memory to prevent the data from being lost when a portion of the cache memory is powered off. Scheduling and implementing a full flush of the cache memory poses challenges because a cache memory flush should not occur if memory buses are being used, and a full cache memory flush can take longer than the duration of a gap in memory bus usage. If a full cache memory flush is scheduled when other operations will need to access the memory bus, the result will be increased latency in accessing the cache memory. To avoid increasing latency, a full cache memory flush cannot be scheduled until it is known that there is time for completing a cache memory flush from beginning to end before the memory bus will be needed again. When operations are accessing the cache memory frequently, this scheduling requirement may result in cache memory flushes occurring infrequently, which can increase the power drawn by the cache memory as the memory fills up with data that is no longer required to be cached.